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DIGITAL AUDIO MOSFET
Features
IRFI4019HG-117P
Key Parameters
150 80 13 4.1 2.5 150
PD - 96274

Integrated Half-Bridge Package Reduces the Part Count by Half Facilitates Better PCB Layout Key Parameters Optimized for Class-D Audio Amplifier Applications Low RDS(ON) for Improved Efficiency Low Qg and Qsw for Better THD and Improved Efficiency Low Qrr for Better THD and Lower EMI Can Delivery up to 200W per Channel into 8 Load in Half-Bridge Configuration Amplifier Lead-Free Package Halogen-Free
VDS RDS(ON) typ. @ 10V Qg typ. Qsw typ. RG(int) typ. TJ max
h
V m: nC nC C
G1 S1/D2 G2 S2
D1
TO-220 Full-Pak 5 PIN
G1, G2 D1, D2 S1, S2
Description
Gate
Drain
Source
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It consists of two power MosFET switches connected in half-bridge configuration. The latest process is used to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery, and internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable device for Class D audio amplifier applications. Absolute Maximum Ratings
h
Parameter
Max.
150 20 8.7 6.2 34 77 18 7.2 0.15 -55 to + 150
Units
V A
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM EAS PD @TC = 25C PD @TC = 100C TJ TSTG
Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
c
Single Pulse Avalanche Energyd Power Dissipation
f Power Dissipation f
mJ W W/C C
Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
300 10lbxin (1.1Nxm)
Thermal Resistance
RJC RJA
h
Junction-to-Case
f
Parameter
Typ. --- ---
Max. 6.9 65
Units
Junction-to-Ambient
f
Notes through are on page 2
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1
10/08/09
IRFI4019HG-117P
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss LD LS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance Internal Drain Inductance Internal Source Inductance
h
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 5.2A VDS = VGS, ID = 50A
Min.
150 --- --- 3.0 --- --- --- --- --- 11 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units
--- 0.19 80 --- -11 --- --- --- --- --- 13 3.3 0.8 3.9 5.0 4.1 2.5 7.0 6.6 13 3.1 810 100 15 97 4.5 7.5 --- --- 95 4.9 --- 20 250 100 -100 --- 20 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- nH --- pF VGS = 0V VDS = 25V ns
V m V mV/C A nA S
V/C Reference to 25C, ID = 1mA
e
VDS = 150V, VGS = 0V VDS = 150V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 50V, ID = 5.2A VDS = 75V
nC
VGS = 10V ID = 5.2A See Fig. 6 and 19
VDD = 75V, VGS = 10VAe ID = 5.2A RG = 2.4
= 1.0MHz, Between lead, 6mm (0.25in.) from package
See Fig.5
VGS = 0V, VDS = 0V to 120V
D
G S
and center of die contact
Diode Characteristics
Parameter
IS @ TC = 25C Continuous Source Current ISM VSD trr Qrr (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
h
Min.
--- --- --- --- ---
Typ. Max. Units
--- --- --- 57 140 8.7 A 34 1.3 86 210 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 5.2A, VGS = 0V TJ = 25C, IF = 5.2A di/dt = 100A/s
e
e
Notes:
Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 5.8mH, RG = 25, IAS = 5.2A. Pulse width 400s; duty cycle 2%.
R is measured at TJ of approximately 90C. Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
Specifications refer to single MosFET.
2
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IRFI4019HG-117P
100
TOP
100
ID, Drain-to-Source Current (A)
10
BOTTOM
ID, Drain-to-Source Current (A)
VGS 15V 12V 10V 9.0V 8.0V 7.0V 6.0V 5.5V
TOP
10
BOTTOM
VGS 15V 12V 10V 9.0V 8.0V 7.0V 6.0V 5.5V
1
5.5V
1
5.5V
0.1
60s PULSE WIDTH Tj = 25C
0.01 0.1 1 10 100
60s PULSE WIDTH Tj = 150C
0.1 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current()
2.0
ID = 5.2A VGS = 10V
10
TJ = 175C
1.5
1
TJ = 25C VDS = 50V 60s PULSE WIDTH
1.0
0.5
0.1 4 5 6 7 8
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
TJ, Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
100000
10000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
ID= 5.2A 16
C, Capacitance (pF)
VDS = 120V VDS= 75V VDS= 30V
1000
Ciss Coss Crss
12
100
8
10
4
1 1 10 100 1000
0 0 5 10 15 20 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
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Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
3
IRFI4019HG-117P
100
100
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on) 1msec 100sec
ISD , Reverse Drain Current (A)
10
TJ = 150C
10
DC 1
10msec
1
TJ = 25C
VGS = 0V
0.1 0.0 0.5 1.0 1.5
Tc = 25C Tj = 150C Single Pulse 0.1 1 10 100 1000
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
10
Fig 8. Maximum Safe Operating Area
5.0
8
VGS(th) Gate threshold Voltage (V)
ID , Drain Current (A)
4.0
6
ID = 50A
4
3.0
2
0 25 50 75 100 125 150
2.0 -75 -50 -25 0 25 50 75 100 125 150
TJ , Junction Temperature (C)
TJ , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
10
Fig 10. Threshold Voltage vs. Temperature
D = 0.50
Thermal Response ( ZthJC )
1
0.20 0.10 0.05 0.02 0.01
R1 R1 J 1 2 R2 R2 R3 R3 C 1 2 3 3
0.1
J
Ri (C/W)
(sec)
Ci= i/Ri Ci= i/Ri
1.508254 0.000814 2.154008 0.111589 3.237738 2.2891
0.01
SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001 0.01
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.1 1 10
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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IRFI4019HG-117P
( RDS (on), Drain-to -Source On Resistance )
EAS, Single Pulse Avalanche Energy (mJ)
0.5
350 300 250 200 150 100 50 0 25 50 75 100 125 150
ID = 5.2A
0.4
ID 0.91A 1.1A BOTTOM 5.2A
TOP
0.3
0.2
TJ = 125C
0.1
TJ = 25C
0.0 4 5 6 7 8 9 10
VGS, Gate-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
*
* * * *
dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
**
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 14. Diode Reverse Recovery Test Circuit for HEXFET(R) Power MOSFETs
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5
IRFI4019HG-117P
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 15a. Unclamped Inductive Test Circuit
Fig 15b. Unclamped Inductive Waveforms
VDS VGS RG
RD
90%
D.U.T.
+
VDS
-VDD
10%
10V
Pulse Width 1 s Duty Factor 0.1 %
VGS
td(on) tr td(off) tf
Fig 16a. Switching Time Test Circuit
Fig 16b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K 20K
S
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 17a. Gate Charge Test Circuit
Fig 17b Gate Charge Waveform
6
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IRFI4019HG-117P
TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))
TO-220 Full-Pak 5-Pin Part Marking Information
AQ & B C ( # DA S DA I 6 AT DA T DC U )@ G Q H 6 Y @ S @ 7 H V I AU S 6 Q A rr ir A r A t y h h A C v AA vAss r h v AA p Bq v A A) r I
TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2009
G 6 I P DU 6 I S @ U I D
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S @ DA DU 8 @ S P B P G @ G 79 HP @8 T AU TP 6G
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